SRAM compiler billed as having world’s smallest memory footprint

Faraday Technology Corporation, a leading ASIC design service and IP provider, announced the enhancement of its memory compiler IP offerings on both UMC 40eHV and 40LP processes. Based on UMC’s leading-edge 40nm bit cell and Faraday’s design optimization on the peripheral circuit, the newly-launched compilers are able to generate memory instances based on the world’s smallest footprint. Especially, the 40eHV SRAM compiler targets at the application of mobile display driver IC for cost competitiveness.

Faraday has led to provide the first SRAM compiler IP once UMC launched 0.213um2 bit cell on 40eHV and 40LP, which shrinks the area by 15%~30% in various instance sizes and configurations compared with the previous smallest bit cell of 0.242um2. Moreover, with Faraday’s optimized design architecture, both the area and power consumption can be further decreased without any performance scarification. In some benchmark, Faraday helps reduce the area by 20% comparing with other handcrafted memory instances with the same 0.213um2 bit cell. The achievement is critical to SRAM size-dominated applications such as Full HD and WQHD display driver IC.

“40nm will be a long life-cycle process; UMC’s 40nm solution shows great competition capability on IP, cost, yield, and production capacity. Therefore, Faraday will keep enhancing the IP portfolio on this process. We believe the enhanced 0.213um2 memory compiler can bring customers immediate and significant benefits,” said Steve Wang, President of Faraday.