USB 3.2 verification IP and test suite for rapid verification of hosts, devices

USB 3.2 enables new hosts and devices with USB Type-C to be designed as multi-lane solutions, allowing for up to two lanes of 5 Gbps or two lanes of 10 Gbps operation, doubling the data rate over the existing USB Type-C cables. It also supports re-timer enhancements. Synopsys, Inc. now offers what they maintain is the industry’s first verification IP (VIP) and UVM source code test suite to support the latest USB 3.2 specification.

“The USB 3.2 specification is an incremental update that defines multi-lane operation for new USB 3.2 hosts and devices with continued use of existing SuperSpeed USB physical layer data rates and encoding techniques,” said Jeff Ravencraft, USB-IF president and COO. “Being first in industry, Synopsys VIP for USB 3.2 strengthens the ecosystem and facilitates early adoption and fast development of higher-performance USB designs.”

Synopsys VC VIP for USB is based on native SystemVerilog/UVM architecture and features built-in comprehensive coverage, verification plan, extensive protocol checks and integration with Synopsys Verdi^®protocol-aware debug for ease of use and increased productivity. Synopsys VIP includes an extensive and customizable set of frame generation, error injection capabilities and comprehensive exception list to generate negative scenarios. In addition, UVM source code test suites are also available to verify features with minimal effort and jumpstart testing of USB designs.

“We continue to collaborate with standard organizations to develop controller, PHY, Verification IP and test suites for the latest protocols and specifications,” said Vikas Gautam, group director of VIP R&D and corporate applications for the Synopsys Verification Group. “By delivering USB VIP and test suites, including early support for the latest USB 3.2 standard, Synopsys enables designers to efficiently design the latest USB devices and subsystems and accelerate verification closure.”

Synopsys VC VIP for USB 3.2 and source code test suites are available today to early access customers. Contact Synopsys for more information regarding the DesignWare USB 3.2 controller and PHY IP solution.