Synopsys introduced its 3DIC Compiler platform to transform the design and integration of complex 2.5 and 3D multi-die system in a package. It provides an unprecedented fully integrated, high-performance, and easy-to-use environment, offering architectural exploration, design, implementation, and signoff with signal, power, and thermal integrity optimizations, all in one solution. With 3DIC Compiler, IC design and packaging teams are enabled to achieve unparalleled levels of multi-die integration, co-design and faster time to convergence.
With insatiable demand for increasing silicon scalability and new system architectures, 2.5 and 3D multi-die integration have become paramount to meet system-level performance, power, area, and cost requirements. An increasing number of factors are driving system design teams to leverage multi-die integration to address new applications such as artificial intelligence and high-performance computing. These applications are driving new packaging architectures like chiplets and stacked-die, in combination with high-bandwidth or low-latency memory to be integrated in a package solution.
With the advent of 2.5D and 3D IC, the IC packaging requirements are much more like IC design requirements such as SoC-like scale, with hundreds of thousands of inter-die interconnects. Traditional IC packaging tools have been integrated, often loosely, with existing IC Design tools. However, they are fundamentally limited in scalability by their data models and begin to break with the more complex design requirements of recent complex 3DIC architectures. In addition, given the disjoint tools and loosely integrated flows, the 3DIC design schedules are unpredictable, long, and frequently non-convergent.
Synopsys’ 3DIC Compiler is built on an IC design data model – enabling scalability in capacity and performance with more modern 3DIC structures. It provides a single environment with planning, architectural exploration, design, implementation, analysis, and sign off – all in one. In addition, 3DIC Compiler sets a new standard in IC packaging usability with its unique and user-friendly visualization capabilities such as 360° 3D view, cross probing, etc. for all views (architecture, planning, design, implementation, analysis, and signoff).
Synopsys has partnered with Ansys, the global leader in multi-physics simulation, to integrate Ansys’ RedHawk family of silicon-proven analysis capabilities with 3DIC Compiler. RedHawk generates highly accurate signal, thermal, and power data which are tightly integrated into 3DIC Compiler for package design. The automatic back-annotation between RedHawk and Synopsys’ 3DIC Compiler enables much faster convergence with fewer iterations than disjoint solutions.