Mentor, a Siemens business, today announced certification for TSMC’s 12nm FinFET Compact Technology (12FFC) and the latest version of 7nm FinFET Plus processes for its Mentor Calibre® nmPlatformand Analog FastSPICE™ (AFS™) Platform. Nitro-SoCTM place and route system is also certified to support TSMC’s 12FFC process technology.
“TSMC is pleased to work closely with Mentor, which continues to increase its value to the TSMC ecosystem by offering more features to its tool flow in support of our new 12nm and 7nm FinFET Plus processes,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “Mentor has been a strategic partner for many years, and with Siemens’ commitment to further investments in Mentor’s electronic design automation (EDA) technologies, we look forward to helping our mutual customers bring to market new and even more amazing IC innovations.”
Mentor enhanced the Calibre nmDRC™ and Calibre nmLVS™ tools for the latest versions of TSMC’s 12nm and 7nm FinFET Plus processes. Mentor worked with TSMC to not only ensure appropriate coverage, but also to optimize the design kits for runtime performance. In addition, TSMC and Mentor worked together to make extreme ultraviolet (EUV) lithography requirements transparent to mutual customers within the Calibre design rule checking (DRC) and multi-patterning software.
Calibre xACT™ parasitic extraction tool is also certified for TSMC’s 12nm v1.0 and the latest version of 7nm FinFET Plus, achieving needed accuracy requirements.
The Calibre YieldEnhancer tool is not only certified for TSMC’s 12nm and 7nm FinFET Plus processes, but Mentor and TSMC are also jointly delivering enhanced use models that optimize fill runtimes, minimize shape removal through engineering change order (ECO) fill, and ensure consistency across all layers using fill-as-you-go methodologies.
The Calibre PERC™ reliability platform is the verification solution for both IP and full-chip reliability analysis. Point-to-point and current density reliability checks are critical for today’s complex, dense chip designs, but completing these checks on very large 12nm and 7nm FinFET Plus designs requires scalability. TSMC and Mentor collaborated to enable a Calibre PERC solution leveraging a new multi-CPU run capability that allows mutual customers to more quickly find and resolve full-chip reliability concerns in their designs.
The AFS platform, including the AFS Mega circuit simulator, is certified for the TSMC 12nm and TSMC 7nm FinFET Plus processes. The AFS platform supports all the required features for TSMC’s design platforms for mobile and HPC applications. Analog, mixed-signal and radio frequency (RF) design teams at leading semiconductor companies worldwide benefit from using the AFS platform to verify their chips designed in the latest TSMC technologies.
Mentor’s Nitro-SoCTM place and route system is certified for TSMC’s 12nm process. In addition to support for 12nm process rules, Mentor enhanced Nitro-SoC’s core engines to meet the new standard cell architecture requirements and design rules for this high-density, power-efficient process. This enables Mentor to deliver its digital implementation flow for the 12nm node.
“Mentor is pleased to be a key element of the TSMC ecosystem,” said Joe Sawicki, vice president and general manager, Mentor Design to Silicon. “This year, TSMC and Mentor are jointly delivering solutions that continue to provide our mutual customers with multiple design avenues to deliver IC innovations for the mobile, high-performance computing, automotive, and IoT/wearable markets.”
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