Chip design IP enables low-latency data comm among SoCs

Synopsys announced the availability of its complete DesignWare Compute Express Link (CXL) IP solution consisting of controller, PHY, and verification IP for AI, memory expansion, and high-end cloud computing system-on-chips (SoCs). The CXL protocol enables low-latency data communication between the SoC and general-purpose accelerators, memory expanders, and smart I/O devices requiring high-performance, heterogenous computing for data-intensive workloads.

Synopsys’ DesignWare CXL IP solution is compliant with the CXL 1.1 specification and supports all three CXL protocols (CXL.io, CXL.cache, CXL.mem) and device types to meet specific application requirements. The CXL IP is built on Synopsys’ DesignWare IP for PCI Express 5.0, which has been adopted by more than a dozen leading semiconductor companies across all key market segments and has demonstrated proven interoperability with a range of products in the ecosystem.

Synopsys’ DesignWare CXL Controller helps designers achieve timing closure at 1GHz and provides a robust 512-bit architecture that supports x16 links for maximum CXL bandwidth. In addition, the CXL Controller offers reliability, availability, serviceability (RAS) capabilities to help maintain data reliability, as well as successfully debug and resolve linkup issues. The 32 GT/s PHY allows more than 36 decibel (dB) channel loss across power, voltage, and temperature (PVT) variations for challenging long-reach applications. The VC Verification IP for CXL verifies I/O, memory access, and coherency protocol features with built-in sequences, checks, and coverage for all link configurations up to 16 lanes and 32 GT/s data rates. SystemVerilog test suites for CXL accelerate verification closure and are available as source code.

Synopsys’ 32G PHY IP for CXL is available now in 16-nm, 10-nm, and 7-nm FinFET processes. The CXL Controller and VC Verification IP for CXL are available now.