Synopsys announced the availability of Design Compiler NXT, the latest innovation in the Design Compiler family of RTL synthesis products. Early adopters have deployed the new technologies in their design flows and are realizing faster runtimes and very tight correlation with Synopsys’ IC Compiler II place-and-route system, leading to shorter, more convergent design cycles. In addition, power and timing quality of results (QoR) improvements are enabling them to develop more competitive products for markets such as artificial intelligence (AI), 5G, and autonomous transportation.
New optimizations in Design Compiler NXT include power-driven mapping and structuring techniques, concurrent clock and data (CCD) optimization, and a new approach to distributed synthesis that does not sacrifice QoR. To deliver tight correlation and superior QoR at the most advanced process nodes, Design Compiler NXT shares a common library and advanced placement technologies with IC Compiler II, in addition to aligned RC, net topology, and density modeling.
“Our continued investment in the Design Compiler family of products has resulted once again in the delivery of breakthrough synthesis innovations,” said Shankar Krishnamoorthy, senior vice president of engineering, Design Group at Synopsys. “Our customers seamlessly deploy Design Compiler NXT in their production flows and quickly realize the benefits of the runtime, QoR, and convergence improvements it delivers.”
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