DDR5 and LPDDR5 design IP said to be most power-efficient yet

Synopsys has announced new DesignWare Memory Interface IP solutions supporting the next-generation DDR5 and LPDDR5 SDRAMs. The DDR5 and LPDDR5 IP significantly increase memory interface bandwidth compared to DDR4 and LPDDR4 SDRAM interfaces, while reducing area and improving power efficiency.

The DesignWare DDR5 IP, operating at up to 4800 Mbps data rates, can interface with multiple DIMMs per channel up to 80 bits wide, delivering the fastest DDR memory interface solution for artificial intelligence (AI) and data center system-on-chips (SoCs). The industry’s first LPDDR5 IP, running at up to 6400 Mbps, provides significant area and power savings for mobile and automotive SoCs with its dual-channel memory interface option that shares common circuitry between independent channels. For additional power savings, the DesignWare Memory Interface IP solutions provide several low-power states with short exit latencies, and offer multiple pre-trained states for dynamic frequency change capability. The DDR5 and LPDDR5 controller and PHY seamlessly interoperate via the latest DFI 5.0 interface, providing a complete memory interface IP solution for high-bandwidth, low-power SoC designs.

The DesignWare DDR5 and LPDDR5 IP solutions support all required features of the DDR and LPDDR specifications, enabling designers to incorporate the necessary functionality into their SoCs:

• Firmware-based training via an embedded calibration processor in the PHY optimizes the boot-time memory training for highest data reliability and margin at the system level. It also allows fast updates to the training algorithms without requiring changes to the hardware
• Decision feedback equalization (DFE) used in the input receivers reduces the impact of intersymbol interference (ISI) to improve signal integrity
• Reliability, availability, serviceability (RAS) features, including inline or sideband error correcting code (ECC), parity, and data cyclic redundancy checks (CRC), reduce system downtime
• Synopsys PHY hardening and signal/power integrity expertise enable faster design completion time and a higher degree of design confidence
• Synopsys VIP for DDR5 and LPDDR5 provides randomized configuration and runtime selection, as well as built-in comprehensive coverage, verification plan, and protocol checks for increased productivity”

The DesignWare DDR5 PHY and LPDDR5 PHY are scheduled to be available in Q1 of 2019, the DesignWare DDR5 Controller and LPDDR5 Controller are scheduled to be available in Q2 of 2019, and the VC Verification IP for DDR5 and LPDDR5 is available now.