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DSP architecture targets 5G Intelligent Radio Access Networks (RAN) and enterprise access points

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CEVA-XC16 DSP architectureCEVA, Inc. announced its powerful DSP architecture, the Gen4 CEVA-XC. This new architecture delivers unmatched performance for the most complex parallel processing workloads required for 5G endpoints and Radio Access Networks (RAN), enterprise access points and other multigigabit low latency applications.

The Gen4 CEVA-XC unifies the principles of scalar and vector processing in a powerful architecture, enabling two-times 8-way VLIW and up to an unprecedented 14,000 bits of data-level parallelism. It incorporates an advanced, deep pipeline architecture enabling operating speeds of 1.8 GHz at a 7nm process node using a unique physical design architecture for a fully synthesizable design flow, and an innovative multithreading design. This allows the processors to be dynamically reconfigured as either a wide SIMD machine or divided into smaller simultaneous SIMD threads. The Gen4 CEVA-XC architecture also features a novel memory subsystem, using 2048-bit memory bandwidth, with coherent, tightly-coupled memory to support efficient simultaneous multithreading and memory access.

The first processor based on the Gen4 CEVA-XC architecture is the multicore CEVA-XC16, the fastest DSP ever made. It is targeted for the rapid deployment of different form factors of 5G RAN architectures including Open RAN (O-RAN), Baseband Unit (BBU) aggregation as well as Wi-Fi and 5G enterprise access points. The CEVA-XC16 is also applicable to massive signal processing and AI workloads associated with base station operation.
The CEVA-XC16 has been specifically architected with the latest 3GPP release specifications in mind, building on the company’s extensive experience partnering with leading wireless infrastructure vendors for their cellular infrastructure ASICs. The previous generation CEVA-XC4500 and CEVA-XC12 DSPs are powering 4G and 5G cellular networks today, and the new CEVA-XC16 is already in design with a leading wireless vendor for their next-generation 5G ASIC.
The CEVA-XC16 offers high parallelism of up to 1,600 Giga Operations Per Second (GOPS) that can be reconfigured as two separate parallel threads. These can run simultaneously, sharing their L1 Data memory with cache coherency, which directly improves latency and performance efficiency for PHY control processing, without the need for an additional CPU. These new concepts boost the performance per square millimeter by 50% compared to a single-core/single-thread architecture when massive numbers of users are connected in a crowded area. This amounts to 35% die area savings for a large cluster of cores, as is typical for custom 5G base station silicon.
The CEVA-XC16 is available for general licensing starting in Q2 2020. For more information, visit https://www.ceva-dsp.com/product/ceva-xc16/.

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