Programs speed FPGA development efforts with programmable hardware accelerators

Achronix Semiconductor Corporation today announced two new programs to enable research institutions, consortia, and companies full access to Achronix’s leading Speedcore eFPGA technology.

Embedded FPGA (eFPGA) technology rapidly is becoming must-have IP for programmable hardware-acceleration for SoC-based CPU-offload that is used in a wide variety of applications including AI/ML, blockchain, network acceleration, SmartNICs, and intelligent IoT. These eFPGA Accelerator programs provide access to preconfigured versions of the company’s Speedcore eFPGA IP and associated development tools to research institutions and test-chip developers wanting to experiment with or prove out new hardware architectures.

Universities, government agencies, and industry consortia often work at the leading edge of technology advancements. Achronix is committed to supporting these types of cutting-edge research projects. Achronix’s new Research eFPGA Accelerator Program will allow researchers to use preconfigured Speedcore eFPGA IP to build programmable hardware accelerators into their SoC research projects. This program also addresses high-performance compute requirements for government agencies, where there is a real need to solve critical security and hardware assurance problems, though they often lack manufacturing volumes to justify the expense of building a custom SoC.

The Test-Chip eFPGA Accelerator program gives companies the ability to incorporate eFPGA IP into their ASICs and SoCs using Achronix’s silicon-proven, preconfigured IP and supporting ACE design tools. Companies across many application segments and geographies want to test their new architectural designs incorporating programmable hardware accelerators that will address high-performance application requirements for compute, networking, and storage platforms. The Test-Chip eFPGA Accelerator Program allows these companies to easily incorporate this silicon-proven, high-performance eFPGA IP into their ASIC and SoC designs, and then fabricate chips for evaluation volumes.

The Achronix Research eFPGA Accelerator Program and the Test-Chip eFPGA Accelerator Program allows research institutions and test-chip developers to easily license Achronix’s Speedcore eFPGA technology. The license includes access to preconfigured, silicon-proven Speedcore eFPGA IP along with the company’s best-in-class ACE design tools. All of the standard Speedcore deliverables are included in these Accelerator programs. The Speedcore IP for these programs are based on TSMC’s 16FF+ process technology.