Toshiba Memory America, Inc. (TMA) announced the development of a prototype sample of 96-layer BiCS FLASH, its proprietary three-dimensional (3D) flash memory, with 4-bit-per-cell (quad level cell, QLC) technology. With this milestone achievement, Toshiba demonstrates its technology leadership in the storage market by delivering technology that boosts single-chip memory capacity to the highest level yet achieved1.
Toshiba’s new QLC BiCS FLASH significantly expands capacity by pushing the bit count for data per memory cell from three to four. The new product achieves the industry’s maximum capacity of 1.33 terabits2 for a single chip, and a 16-die stacked architecture in a single package realizes an unparalleled capacity of 2.66 terabytes.
The number of applications needing huge amounts of storage continues to grow, fed by the enormous volumes of data being generated that need to be accessed and analyzed in real time. Social media, SSDs, edge computing, enterprise applications and the rapidly expanding data center storage market are all areas in which larger capacity storage is required – to name just a few. With the introduction of 96-layer QLC technology, Toshiba Memory enables the development of products that keep pace with the fast-moving storage market.
QLC technology has long been a part of Toshiba’s roadmap strategy for high-density, smaller chip size flash memory solutions: the company was the first to publicly discuss QLC technology (at the 2016 Flash Memory Summit) and one of the first to develop a 3D flash memory device that uses it.
“We were among the first in the industry to envision and prepare for the successful migration of SLC technology to MLC, from MLC to TLC, and now from TLC to QLC,” noted Scott Nelson, senior vice president of TMA’s Memory Business Unit. “This technology evolution has made increasingly dense packaging options available, and QLC will have a game-changing impact across many different markets.”
Samples of Toshiba’s groundbreaking QLC device will begin shipping in early September to SSD and SSD controller vendors for evaluation and development purposes. Mass production is expected to begin in 2019. Additionally, a packaged prototype will be showcased at the 2018 Flash Memory Summit, taking place from August 6-9 in Santa Clara, California.