SoC design software runs analysis of peak power use

Synopsys, Inc. today introduced PrimePower, an expanded power analysis solution created to accelerate system-on-chip (SoC) design closure by extending signoff power analysis to drive early design implementation and accurate reliability analysis. Revolutionary technologies based on Synopsys’ golden PrimeTime static timing analysis and signoff empower designers to perform faster and uniquely accurate power analysis and power-driven optimizations earlier in the implementation phase with RTL simulation vectors. PrimePower’s native interface with Synopsys’ ZeBu emulation system provides a comprehensive system-level-to-signoff power analysis solution, enabling designers to efficiently and accurately pinpoint and fix power and reliability issues to achieve robust design closure.

Reliability has emerged as a critical requirement in advanced-node designs, where aggressive transistor scaling, decreased voltage margins, and increased power have made reliability analysis a much more significant issue in design. PrimePower addresses the increased reliability concerns at sub-7-nanometer (nm) nodes by expanding power and reliability signoff and engineering change order (ECO) closure capabilities from physical awareness to cell electromigration (EM) effects. PrimePower’s native integration with PrimeTime enables concurrent signoff timing, power, and reliability ECO for single-pass design closure. In addition, its timing and power interfaces enable efficient reliability signoff analysis and deliver robust SoC designs with improved endurance for high-intensive computing tasks throughout the design life cycle.

“HiSilicon builds AI-enabled SoCs on leading-edge semiconductor processes. These SoCs perform the most compute-intensive tasks throughout their service life,” said Huatao Yu, senior manager of worldwide physical design at HiSilicon. “PrimePower enabled advanced reliability modeling and unique signoff-driven auto-fixing in our design flow, saving us weeks of design iterations while enabling lifetime robustness for these intelligent chips.”

The new PrimePower solution strengthens the Synopsys Design Platform by not only enabling early RTL-based analysis and optimizations, but also providing a single DNA backbone for power analysis throughout the digital low-power design flow, from physical implementation to signoff. A key component of the recently announced Fusion Technology solution, PrimePower signoff technology in the Synopsys Design Platform delivers out-of-the-box perfect correlation and best-in-class design power quality of results (QoR) for enhanced SoC performance, power, and area (PPA) closure.

“Emerging technologies such as artificial intelligence, visual computing, and virtual reality are driving innovation for power and reliability of advanced chips,” said Michael Jackson, corporate vice president of marketing for the Design Group at Synopsys. “PrimePower connects signoff power and reliability-driven design optimization with system emulation, augmenting Synopsys’ low-power design portfolio and enabling an efficient path to robust chip designs that can endure real-world compute-intensive scenarios, such as AI self-driving or mobile-VR game play simulations.”