
Alphawave Semi is set to revolutionize connectivity with its Gen3 64 Gbps UCIe IP, delivering a bandwidth density of over 20 Tbps/mm, with ultra-low power and latency. This solution is highly configurable supporting multiple protocols, including AXI-4, AXI-S, CXS, CHI, and CHI-C2C to address the growing demands for high-performance connectivity across disaggregated systems in High-Performance Computing (HPC), Data Centers, and Artificial Intelligence (AI) applications.
The design complies with the latest UCIe Specification and has a scalable architecture with features for advanced testability, including live per-lane health monitoring, making it a robust foundation and enabling an open and interoperable chiplet ecosystem.
UCIe D2D interconnects facilitate a range of standard and emerging chiplet connectivity scenarios. Common uses encompass linking compute chiplets for a low-latency, coherent connection via UCIe’s streaming capabilities, as well as connecting compute to I/O chiplets using UCIe interfaces with PCIe, CXL, or Ethernet. Additionally, optical retimers can leverage the UCIe chiplet architecture to establish dependable, low-latency optical I/O links through optical engines, enhancing off-system connectivity. This supports the development of low-power, high-speed solutions in data centers and AI/ML systems.
For high performance applications, creating a custom HBM base die using the latest UCIe standard is a cutting-edge approach that involves tightly integrating memory dies with compute dies to achieve extremely high bandwidth as well as a low latency between the components. This allows for reuse of die-to-die shoreline already occupied on the main die for core-to-core or core-to-I/O connections. This approach greatly optimizes memory transactions in AI applications where low power and reduced latency are performance differentiators.
This achievement, alongside Alphawave Semi’s earlier industry-first 3nm silicon-proven Gen1 UCIe IP, reaffirms the company’s rapid progress as a leader in high-performance chiplet connectivity solutions with a full suite of silicon-proven connectivity IP subsystems tailored for hyperscaler and data-infrastructure markets.
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