QuickLogic Corporation has released a new version of its Aurora eFPGA development tool suite. The Aurora 2.1 Development Tool Suite is based on a fully open-source implementation for scalability, longevity, and full code transparency. It supports all major HDLs including Verilog, System Verilog, and VHDL.
The new version is based on open-source synthesis (Yosys), Versatile Place and Route (VPR), and bitstream generation (OpenFPGA) software. The fully integrated suite of tools enables FPGA designers to go from RTL-to-bitstream for QuickLogic’s eFPGA IP. The Aurora eFPGA user tools also support an architecture analysis mode, enabling users to tune the architecture for their application instead of being forced into a ridged fixed-size tile approach.
Key Benefits include: Enables Architectural Trade-Offs – Ensures that the generated eFPGA IP has the optimal amount of logic (LUTs), BRAM, and DSP blocks to meet each customer’s unique eFPGA requirements; More Transparency – Because Aurora is based on open source, the code is highly inspectable, enabling continuous improvement by the development community; Flexibility – Publicly auditable code leads to higher quality software and allows for the merit-based addition of features by the community, as well as the option to make enhancements that suit each customer’s needs; Future-Proof – Aurora uses readily available open-source components that the broader community is actively improving upon. With access to source code, the user has ultimate control of the future;
QuickLogic’s new Aurora 2.1 Development Tool Suite is available now.
