Synopsys announced it has delivered silicon-proven HB
M2E PHY IP operating at 3.2 gigabits per second (Gbps), addressing high throughput requirements of advanced graphics, high-performance computing and networking SoCs. Verified on TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) advanced packaging technology, Synopsys’ DesignWare HBM2E PH
With an aggregated bandwidth of 409 gigabytes per second, the HBM2E PHY delivers the required massive compute performance of system-on-chips (SoCs) in advanced FinFET processes. The HBM2E IP is part of Synopsys’ comprehensive memory interface IP solution that includes DDR5/4/3/2 and LPDDR5/4/3/2 IP, which have been validated in hundreds of designs and shipped in millions of SoCs.
The Synopsys DesignWare HBM2/2E IP is available now.