ADCs with SDR help reduce design efforts and let designers focus on implementing more fashionable features.
Ryan Liu | Microchip Technology Inc.
Software-defined radio (SDR) technology finds its way into everything from multi-carrier multi-standby smartphones to innovative multi-mode mobile internet electronics. When enabled by SDR, a configurable transceiver works flexibly with software-defined carrier frequencies, easing the task of RF design.
For many years, the evolution of wireless communication standards depended on large-scale hardware upgrades. Today, however, the adoption of SDR technologies makes it easier to find alternatives to expensive hardware.
The primary motivation of the SDR concept is to overcome added costs. The three essential methods used in SDR are to move the broadband analog-digital conversion (ADC) and digital-to-analog converter (DAC) as close as possible to RF devices, use hardware as the basis of wireless communication, and maximize software options to enable functions that are traditionally only available in the RF and intermediate frequency (IF) analog domain.
To make the system more flexible at a lower cost, items such as the operating frequency band and modulation method are configured by software in the digital domain. SDR lets the same hardware handle multiple frequency bands by loading the relevant software as required. This scheme works for products ranging from smartphones to sensor networks. Meanwhile, market forces are driving the steady development of high-speed, high-precision ADC technology to enable fast and accurate processing of wireless broadband signals. ADC limitations previously constituted one of the main bottlenecks to SDR.
Receiver design is a critical priority for SDR. So it is useful to review the special requirements for SDR receiver implementation. The key is the front-end. Implementation of the entire SDR system dictates how to partition specifications for the ADC and other key components. High speed, dynamic range, and richness in software configurations are essential in the ADC.
SDR receivers generally can be divided into three categories based on their signal bands: RF sampling receivers, IF sampling receivers, and baseband sampling receivers. RF sampling most resembles the ideal SDR structure: An ADC connected to an antenna to form a receiver and a DAC connected to an antenna to form the transmitter. However, the two major performance bottlenecks — RF devices and ADCs — make the ideal structure the most difficult to realize at a reasonable cost.
Among structures in the other two categories, the most widely used are zero IF receivers, low IF receivers, and bandpass sub-sampling high IF receivers. As a quick review, a zero-IF receiver (also known as a direct conversion receiver) demodulates the radio signal using synchronous detection driven by a local oscillator (LO) whose frequency is identical to that of the carrier frequency of the signal being demodulated. In low IF receivers, the RF signal is mixed down to a non-zero low or moderate IF, usually in the range of a few megahertz to a few hundred kilohertz. In sub-sampling receivers, the RF signal is sampled using a frequency lower than twice the maximum input frequency but larger than twice the signal bandwidth. One of the low-frequency replicas resulting from the sampling process, which contains the baseband signal, is then directly digitized.
When the ADC is placed after the mixer, the performance constraints are the lowest for ADC in zero IF receivers. Because LO frequency (fLO) and the RF signal central frequency into the mixer (fRF) are the same, the ADC need only process the signals in the baseband. Ideally, there are no image interferences. Therefore, an image rejection filter is unnecessary, eliminating the need for expensive surface acoustic wave (SAW) filters. However, the biggest challenge of zero IF is that either dc offset and orthogonal errors are unavoidable, or the calibration algorithm is overly complex, especially when implemented using discrete components.
The dc offset typically originates from a non-ideal mixer. The mixer LO signal leaks and loops back into the receiver signal path (known as the LO leakage) through parasitics. It is also amplified by the transmitter antenna in that loop. Because this interference changes amplitude with the transmitter amplification – and the frequency is equal to fLO in the receiver – the time-variant dc offset is generated at the mixer output. Adjacent objects passing the antenna will further complicate the situation. DC offset can lead to severe overloading; in other words, it can form a strong blocker at the signal center frequency.
Orthogonal error is primarily caused by mismatched inherent errors between channels. The situation is especially challenging in discrete structures, as it results in image interference and deteriorating constellation specifications like Inter Symbol Interference (ISI). In scenarios such as 64 quadrature amplitude modulation (QAM) for the LTE standard, the higher the modulation efficiency, the more the jitter can degrade the SNR.
In low IF receivers, the ADC bandwidth must be twice that in zero IF architecture. Low IF receivers use an fLO which has a slightly lower-Q filter specification from fRF. This solves the dc offset problem and controls LO leakage. While orthogonal error and mismatch are still issues with this structure, a low IF SDR with balanced block specifications is more economical and effective than zero IF designs.
The third widely used structure is bandpass sub-sampling high IF receivers, commonly known as high IF. The ADC must work at a higher frequency than in zero IF or low IF receivers. Modern ADC technology makes this design feasible at a reasonable cost.
One methodology for implementing a low IF or high IF receiver is to combine a superheterodyne front end with a highly digitized back end. It is vital to emphasize that this no longer sticks to the strategy of a fixed IF frequency as in a traditional superheterodyne structure. Instead, it fully allows the software to tune the channel parameters and thereby overcome the superhet’s traditional disadvantage of being able to tune to only a narrow band of frequencies.
Both low IF and high IF receiver approaches need down-conversion and thus a mixer. Digital mixers often take the form of a numerically controlled oscillator (NCO). With an NCO the In-phase/Quadrature (I/Q) signal frequency can be accurate regardless of the LO frequency. These types of mixers can handle a broader band of frequencies than their analog counterparts. Signals will not have dc offset or obvious image interference, even when down-converted to dc. The combination of digital mixers, oscillators, and decimation filters is generally referred to as a digital down-converter (DDC).
Challenges on the circuit level
The overall performance of an SDR made with discrete components can be compromised by the number of devices involved and PCB-level imperfections.
The discrete scheme requires careful thought about non-ideal factors such as random noise, dynamic interference, and channel-to-channel mismatch. The clock jitter mismatch is a mismatch between channels, and it directly degrades the SNR metrics in modulation methods mentioned earlier.
PCB-mounted components can also introduce a lot of thermal noise and electromagnetic interference (EMI). EMI rejection is closely related to the EMI source, place, routing, shielding and filtering – most of which are difficult to control. Fast protocol speed, a complex environment, and higher switching power supply energy can also contribute to EMI. In-channel clock jitter error can degrade the accuracy of the sampling instant and therefore the sampling accuracy.
Additionally, the down-conversion and the mixer also need careful design. Some manufacturers implement entire DDCs in either FPGAs or ASIC digital signal processor (DSP) chips. Although some perform well, they are not as economical as alternatives.
Such difficulties can be improved significantly through use of integrated designs. The overall approach is to digitize everything possible, with discrete components only handling functions that cannot be defined through software.
To develop an integrated SDR, high-speed, high-precision, low-power ADCs with dynamic performance and integrated features are ideal for low IF and some bandpass high IF receiver applications. An example is the MCP37Dxx ADC series from Microchip Technology. It offers 16-, 14-, and 12-bit resolution, saving power and supporting a sampling rate up to 200 MHz. It also allows input signal bandwidth up to 500 MHz.
The MCP37Dxx has built-in features that do not require a FPGA or dedicated DSP. These include DDC, NCO, a digital decimation filter, a noise-shaping requantizer, gain adjustment, and offset adjustment. DDC can be used with the decimation and quadrature output (I/Q data) option. It offers flexibility in SDR radio system designs, minimizes system cost and helps improve SNR beyond conventional resolutions. It supports up to eight input channels with input multiplexers. In dual or octal mode, the fractional delay recovery (FDR) function digitally deskews data between different channels so all inputs are interpolated to appear sampled at the same instant. The output data is available as full-rate CMOS or double data rate (DDR) LVDS. In some devices like the MCP37D31-200, the output also supports serial LVDS in eight-channel mode.
Digitally enhanced high-speed ADC for low power wireless applications, Thomas Youbok Lee, et al., ICMIM, IEEE, 19-21 March 2017
Software-defined radio tunes in, D. Marsh, EDN, March 2005, p. 5234