MCU vs FPGA — What’s the diff?

FPGAs are highly configurable, general purpose integrated circuits (ICs) filled with small programmable digital logic building blocks called “logic cells” (by Altera) or “logic elements” (by Xilinx). A custom IC, or Application Specific Integrated Circuit (ASIC), is very similar but with ASICs, a custom circuit design is set in silicon and is difficult to change after the fact (las

ers can affect some changes in circuits on ICs after manufacture and before packaging, however.) ASICs offer hardware-based solutions and are the ultimate choice in custom hardware designs to achieve specific application goals.

FPGAs stand somewhere in between microcontrollers (MCUs) and ASICs in terms of versatility and capability. However, as FPGAs have decreased in price and have been combined with processors in the same platform, the lines are starting to blur between ASICs and FPGAs. FPGAs are less flexible to program than MCUs but offer an exactness in customization through hardware that is not possible with MCUs, such as customized hardware-acceleration for algorithms.

Some FPGAs are one-time programmable, but most FPGAs can be reconfigured or updated after deployment, to the point of being dynamically reconfigured in a computing application.[i] According to Xilinx, “Partial Reconfiguration is the ability to dynamically modify blocks of logic by downloading partial bit files while the remaining logic continues to operate without interruption.”[ii]

FPGAs can execute scores of computations with low latency. FPGA programming involves a steep learning curve. MCUs are easier to use in development as design iterations are tested. FPGAs must do more than just “recompile;” the FPGA must re-place and re-route with changes.

MCUs have greater portability of design than FPGAs. FPGAs most often employ fixed-point operations. FPGAs are capable of sophisticated, time-critical signal processing with strict throughput and low latency requirements because dedicated hardware and memory can ensure time guarantees.

FPGAs are now offered with processor cores for a hybrid approach. The learning curve with FPGAs is one of the greater barriers to developing with FPGAs. Unfamiliarity with FPGAs and programming them leads to a bias towards solving problems with an MCU. Nevertheless, FPGAs cannot be avoided applications with stringent computational and memory requirements, such as imaging or with applications that require a high level of determinism, with extremely fast throughput and low latency.

Table 1: Some fundamental differences between FPGAs and MCUs.

	MCU	FPGA
Learning Curve	Learning curve with some cross-over in tools (e.g. the ever more widespread Eclipse IDE, shared languages).	Steeper learning curve
Fixed/Floating point operations available	Fixed and floating point are widely available.	Mostly fixed point. Difficult to accommodate floating point.
Time-critical processing	Depends on requirements as to whether the MCU can accommodate. Limited reach.	Capable of sophisticated, time-critical signal processing with strict throughput and low latency requirements.
Portable design	Easier to port designs between MCUs with C/C++ language.	No universal design method that is portable.
Total Flexibility	Reprogramming software only.	Superior in software and hardware flexibility in customization. Dynamic reconfiguration is possible.
Development Angst	Code changes can often be added after compilation like a patch, without re-compiling, for a facile development process.	Development iterations take longer with re-placing and rerouting required of FPGAs in the development process.
Tools	Open source tools increasingly make the development process portable across platforms.	No portability across tools. Universal design methods are non-existent.

 

[i] Pellerin, David, and Scott Thibault. Practical FPGA programming in C. Upper Saddle River, NJ: Prentice Hall Professional Technical Reference, 2005. Print.

[ii] “Partial Reconfiguration in the Vivado Design Suite.” Partial Reconfiguration in the Vivado Design Suite. N.p., n.d. Web. 18 Dec. 2016.