IC place-and-route software boasts speedy runtime

Siemens Digital Industries Software announced that the latest release of its Aprisa physical design solution is now available. Aprisa 21.R1 has achieved major performance and technology advancements, including dramatic improvements in both runtime and memory footprint reductions. For customers, these enhancements can translate to lower design costs and faster time-to-market.

The technology advancements available in Aprisa 21.R1 demonstrate Siemens’ commitment to delivering best-in-class physical design Integrated Circuit (IC) solutions to its Electronic Design Automation (EDA) customers. Since completing the acquisition of the Aprisa portfolio in December 2020, Siemens has more than doubled the Aprisa R&D team as part of a substantial investment in the Aprisa technology portfolio.

The latest release of Aprisa targets advanced technology nodes and includes the following milestones and highlights:

• Average full-flow runtime reduction of 30 percent compared to the previous release, and up to 2X faster runtimes for larger, more challenging designs.
• Enhancements to all major place-and-route engines, from placement optimization to clock tree synthesis (CTS) optimization, route optimization and timing analysis. The benefits of these performance enhancements can be observed on almost all IC designs, and especially on large designs with complicated multi-corner multi-mode (MCMM) features. On these challenging designs, Aprisa has proven to run up to 2X faster than the previous generation.
• Up to 60 percent memory footprint reduction; Aprisa has reduced, on average, 30 percent full-flow peak memory usage for large designs, and up to 60 percent for complex designs, compared to the previous generation. This greater efficiency enables even larger designs with complicated MCMM to be completed on servers with less available RAM.
• 6nm/5nm/4nm design enablement. Siemens has collaborated closely with leading foundries to enable Aprisa for advanced nodes. Aprisa is fully certified for 6nm processes, and Siemens has implemented all required design rules and features for the design enablement of 5nm and 4nm nodes. Final certifications, in collaboration with the world’s leading foundry partners, are in progress.
• Extended support for multi-power domain (MPD). The extended functionalities greatly increase the flexibility and completeness of MPD support, which is critical for extreme low-power designs.