MIPI C/D-PHY combo IP core complies with MIPI C-PHY v2.0 and D-PHY 2.5 specs

Arasan Chip Systems announces the immediate availability of its MIPI C-PHY/ D-PHY Combo IP which is compliant with the latest MIPI C-PHY v2.0 and MIPI D-PHY v2.5 specifications. The upgraded MIPI C-PHY / D-PHY Combo IP is seamlessly integrated with Arasan’s own MIPI CSI-2 IP and MIPI DSI IP as part of Arasan’s Total IPTM for MIPI Imaging and Display Solutions. This 2nd generation of Arasan’s MIPI C-PHY/D-PHY combo IP has been re-engineered for ultra-low power consumption leveraging the advantages of the FINFET Technology.

Arasan’s MIPI C-PHY v2.0 / D-PHY v2.5 combo IP delivers 6 Gbps per lane for a max throughput of 24Gbps in D-PHY mode and 6Gsps per trio for a max throughput of 41Gbps in C-PHY mode. Other significant feature upgrades include: When used with Arasan’s  MIPI CSI-2 or MIPI DSI-2, the MIPI C-PHY/D-PHY combo IP offers built-in test capabilities including PRBS generator and internal loopback to support cost-effective tests for high volume manufacturing; New power-saving HS-Tx half swing mode for D-PHY; On-board programmable PLL with Spread Spectrum Clocking, with or without deskew calibrations and equalizations for different operating speeds of D-PHY, Power management functions such as reduced HS-TX swing modes and unterminated HS-RX mode; It supports ALP Mode for different applications with long channels that enables fast lane turnaround mode to increase the bandwidth of communication in the reverse direction of the MIPI link. The ALP mode is key to the CSI-2 Unified Serial Linking capability, which decreases interface wires and helps to allow a more extensive range.