sureCore continues developing technologies to reduce SoC power consumption thereby enabling developers to extend battery lives. Its latest innovation is MiniMiser that reduces the power consumption of register files by over 50%. Register files are small blocks of memory that typically interface directly to high-performance logic to provide fast access to data needed for calculations. These are often located inside the related compute blocks to reduce wiring delays and ensure both power and performance targets can be met. Their activity level directly matches that of the logic they are coupled to – hence their power requirements can contribute significantly to the overall power budget of the chip. To address this sureCore has developed MiniMiser to cut register file power consumption in next-generation, battery-powered devices where extending recharge cycle times is paramount.
Ultra-low-power register file memory targets AI-intense portable devices
sureCore first delivered an SRAM capable of similarly offering a wide operating voltage range over 4 years ago which developers have taken advantage of for identical reasons. In that case, the memory is based on the foundry bit cell with the company’s patented SMART-Assist technology ensuring the bit cell is always operated in the foundry recommended voltage window.
The MiniMiser architecture is based on a customized storage element and exploits sureCore’s SRAM power-saving techniques to deliver significantly improved power characteristics even at nominal process voltages. The architecture lends itself to several optimization criteria – multi-port and high-performance variants can be readily generated by the company’s powerful proprietary compiler technology. As MiniMiser is not based on the foundry bit cell than its yield characteristics, like the logic, follow the process d0 thereby easing DFT considerations.
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