Near-memory accelerators interoperate with AMD EPYC CPUs and 5th Gen Intel Xeon platforms

Marvell Technology, Inc. announced the successful interoperability of the Marvell Structera portfolio of Compute Express Link (CXL)with AMD EPYC CPUs and 5th-generation Intel Xeon platforms. This achievement underscores Marvell’s commitment to advancing an open and interoperable CXL ecosystem, addressing the growing demands for memory bandwidth and capacity in next-generation cloud data centers.

Marvell collaborated with AMD and Intel to extensively test Structera CXL products with AMD EPYC and 5^th Gen Intel Xeon Scalable platforms across various configurations, workloads, and operating conditions. The results demonstrated seamless interoperability, delivering stability, scalability, and high-performance memory expansion that cloud data center providers need for mass deployment.

This interoperability gives customers the flexibility to choose from a variety of CPU architectures, enabling deployment of CXL solutions across diverse hardware configurations. By leveraging the strengths of each platform for specific workloads and applications, customers can maximize their investment while maintaining seamless integration and consistent performance.

The Structera product family, built on CXL 2.0, enables cloud service providers and server OEMs to dramatically increase the memory capacity and bandwidth of servers or add additional computing cores to improve the performance and capabilities of cloud servers efficiently and economically. Structera can also add computing cores for offloading memory-intensive applications such as artificial intelligence, machine learning, in-memory databases, and high-performance computing.

Key products within the Structera portfolio include:

Structera A: Near-memory accelerators featuring server-class Arm Neoverse V2 cores, DDR5 support, and up to 1.6 Tbps of memory bandwidth, optimized for high-bandwidth workloads such as deep learning recommendation models (DLRM).

Structera X: Memory expansion controllers supporting DDR4 and DDR5 DIMMs, enabling the deployment of terabytes of memory capacity while optimizing both cost efficiency and power consumption.

The integration of CXL 2.0 technology enables cache coherency and memory pooling across devices, optimizing resource utilization, reducing the need for additional servers, and promoting sustainable data center architectures.