RISC architecture and instruction architecture

RISC stands for Reduced Instruction Set Computer and is a type of architectural processor design strategy. “Architecture” refers to the way a processor is planned and built and can refer to either the hardware or the software that is closest to the silicon on which it runs. An Instruction Set Architecture (ISA) specifies the basic software (instruction set) for an architecture. A common question might be: “What is the ISA for that computer/tablet/smartwatch?” with a response of something like, “It has an ARM Cortex-M8 core CPU.” (Core means the processor engine only, e.g., no peripherals. ARM Holdings, Inc., holds an acronym that stands for Acorn RISC Machines.) The ISA provides functions to a higher layer of software above it.

The hardware architecture of a computer requires code that breaks instructions down into 0s and 1s that the machine can understand; also known as machine code. Processor architectures can be quite different, and the ISA software will reflect that. The difference between architectures can be found in how tasks are completed, such as how a specific architecture handles registers, interrupts, memory addressing, external inputs and outputs, and so forth.

In other words, machine code for one architecture will not work on another. For example, a desktop version of Windows will not run on a smartphone, since the architectures are different. (Although Microsoft seems to be encouraging an eventual merging to a single OS for desktops, laptops, and tablets, starting with the introduction of Windows 8.) Several types of processor architectures and corresponding ISAs exist. Some examples of RISC processor architectures are the ARM, MIPS, SPARC, and PowerPC.

In a different camp is the Complex Instruction Set Computing (CISC) architecture, which preceded RISC. As the name implies, with the CISC architecture a single instruction can execute several operations in one clock cycle. The original goal of CISC was to produce fewer lines of assembly code. The x86 is a CISC-based architecture. One advantage of CISC is in using C code. All other things being equal, C code translates to more lines of RISC assembly code than does CISC. Therefore, x86 is more efficient with respect to the use of C code.

However, the RISC architecture was developed with an eye to reducing complexity by using a simpler instruction set on processors that clock fewer cycles per second. RISC is a Von Neumann type architecture. Von Neumann architectures can be categorized as the type that reads and executes one instruction at a time, which makes it possible to set up a predictable “pipeline” of instructions (or bottleneck, depending on your point of view). Pipelining makes it easy for processing in parallel, e.g., multicore processing. Early on, RISC found a place in embedded processors due to an instruction set that did not take up much space, its real-time processing capability, and low power consumption. The disadvantage for RISC was a lack of software to run on the RISC instruction set; the market simply was not there, so RISC suffered a lack of mainstream commercial adoption.

Today’s processors are highly integrated and faster, such that RISC instruction sets are becoming more complex so as to take advantage of improved technology. In fact, RISC and CISC instruction sets are becoming more alike than not as advances begin to blur the delineation between the two. Nevertheless, it’s a good idea to know the history behind the architectures, why they were created, and how they evolved.