Synopsys announced general availability of the VC SpyGlass RTL Static Signoff platform, part of the Synopsys Verification Continuum platform, which builds on the proven SpyGlass technology. The VC SpyGlass platform with multi-core support increases performance by 3X with half the memory footprint. The next-generation platform is enhanced with machine learning technology to reduce noise by 10X with no loss in quality of results using trusted industry-standard SpyGlass engines.
Increasing SoC complexity demands verifying correct construction of RTL, clock domain crossing (CDC), and reset domain crossing (RDC) early in the RTL phase of development. Synopsys VC SpyGlass integrates advanced algorithms and analysis techniques that provides designers detailed information and insights about their design much earlier in the RTL phase. It provides a tightly integrated solution for formal-enabled linting to reduce noise and comprehensive CDC and RDC analysis to catch logic issues added during implementation. VC SpyGlass is also natively integrated with Synopsys’ Verdi automated debug system to accelerate root cause analysis for bugs. In addition, the VC SpyGlass platform uses design behavior and Tcl flow consistent with Synopsys’ Design Compiler and PrimeTime® tools to significantly reduce setup time between implementation and verification flows.
“Insufficient or incorrect constraints are the primary reason for a large number of violations, which increases our debug cycles,” said Hideyuki Okabe, director of the Digital Design Technology Department, Shared R&D Division, IoT and Infrastructure Business Unit at Renesas Electronics Corporation. “The new machine learning technology in VC SpyGlass will help our design teams to significantly reduce the number of false CDC violations to debug, enabling much faster identification of root cause.”
The Synopsys VC SpyGlass RTL static signoff platform is available now. Current SpyGlass users can easily upgrade to VC SpyGlass, using existing rules and scripts.