The winners of the 2020 LEAP Awards (Leadership in Engineering Achievement Program) were announced last week in a digital ceremony, with products across 12 categories, including embedded computing, power electronics, and test and measurement. Critical to LEAP’s success is the involvement of the engineering community. No one at WTWH Media selected the winners. Instead, our editorial team did the arduous work of assembling a top-notch independent judging panel, comprised of a cross-section of OEM design engineers and academics — 14 professionals in total. This judging team was solely responsible for the final results.
In the Embedding Computing category, Xilinx took home the gold with their Versal AI Core, the first Adaptive Compute Acceleration Platform (ACAP), is a multi-core, heterogeneous compute platform that dynamically adapts at the hardware and software level for a wide range of applications and AI workloads from edge to cloud. The platform integrates next-generation scalar engines for embedded compute, adaptable engines for hardware programmability, and intelligent AI Engines and DSP Engines for AI inference and signal processing.
The architecture is unique as it solves the most difficult problem of AI inference—compute efficiency—by coupling ASIC-class compute engines (AI engines) with adaptable hardware to implement custom memory hierarchy and custom neural network layers. Versal AI Core breaks through traditional compute bottlenecks, specialized hardware customization without manufacturing a new chip. The AI Engine delivers 8X the compute density at half the power of traditional FPGA solutions and delivers low-latency Convolutional Neural Network (CNN) execution 3.5X faster vs. traditional GPUs.
The adaptability and heterogeneous architecture of Versal AI Core is a key advantage over traditional AI accelerators that typically focus on a subset of AI workloads. AI algorithms are diverse across industries—from cloud computing to networking, to edge and autonomous system. The adaptable nature of Versal AI Core makes it applicable for a breadth of markets.
Commenting on the Versal AI Core, judges said: “A game changer for the next generation of networking electronics, medical imaging diagnostic instruments and any application needing state-of-the-art processing power.”
Picking up the silver award was Texas Instruments Jacinto 7 processor platform that brings enhanced deep learning capabilities and advanced networking to solve design challenges in ADAS and automotive gateway applications. The TDA4VM processors for ADAS and DRA829V processors for gateway systems are the first two devices in the portfolio. These devices include specialized on-chip accelerators designed to segment and expedite computer vision, deep learning and other data-intensive tasks, allowing the car to more accurately perceive and react to the world around it.
Supporting sensor fusion from cameras, LIDARs, radars and other sensors, the Jacinto 7 devices are able to accept inputs from multiple sources to not only create the most accurate vision of the world around the car, but also to utilize machine learning intelligence to help the car and driver best react to that world. Designed for L2 and L3 automated functions, these devices are targeted for applications ranging from automatic emergency braking and lane-keep assist to more accurate autonomous parking and highway autopilot.
Finally, the bronze went to Lattice Semiconductor for their CrossLink-NX FPGA, the FPGA developed on the Lattice Nexus FGPA platform, the industry’s first 28nm FD-SOI-based FPGA platform optimized for low power operation in a small form factor. The CrossLink-NX FPGA provides the energy efficiency, small form factor, high reliability and high-performance developers in communications, compute, industrial, automotive, and consumer markets need to enable innovative embedded vision solutions for the Edge. These new chips are designed to address the latest trends in video processing: mixing multiple sensors and displays, higher resolution video, multiple interfaces, and Edge AI processing.
CrossLink-NX consumes 75 percent less power compared to competing FPGAs of a similar class. In addition, CrossLink-NX has a Soft Error Rate (SER) up to 100 times lower than similar FPGAs in its class, making it a compelling solution for mission-critical applications that must operate safely and reliably. The initial CrossLink-NX device is designed to support ruggedized environments found in outdoor, industrial, and automotive applications. CrossLink-NX delivers Instant on performance. This enables ultra-fast I/O configuration in 3 ms and total device configuration in less than 15 ms. It is available in a 6 x 6 mm form factor, which is up to ten times smaller than similar competing FPGAs in its class.
Xilinx, Inc. announced Versal Premium, the third series in the Versal ACAP portfolio. The Versal Premium series features highly integrated, networked and power-optimized cores and the industry’s highest bandwidth and compute density on an adaptable platform. Versal Premium is designed for the highest bandwidth networks operating in thermally and spatially constrained environments, as well as for cloud providers who need scalable, adaptable application acceleration.
Versal is the industry’s first adaptive compute acceleration platform (ACAP), a revolutionary new category of heterogeneous compute devices with capabilities that far exceed those of conventional silicon architectures. Developed on TSMC’s 7-nanometer process technology, Versal Premium combines software programmability with dynamically configurable hardware acceleration and pre-engineered connectivity and security features to enable a faster time-to-market. The Versal Premium series delivers up to 3X higher throughput compared to current generation FPGAs, with built-in Ethernet, Interlaken, and cryptographic engines that enable fast and secure networks. The series doubles the compute density of currently deployed mainstream FPGAs and provides the adaptability to keep pace with increasingly diverse and evolving cloud and networking workloads.
The Versal Premium series is built on a foundation of the currently shipping Versal AI Core and Versal Prime ACAP series. New and unique to Versal Premium are 112Gbps PAM4 transceivers, multi-hundred gigabit Ethernet and Interlaken connectivity, high-speed cryptography, and PCIe® Gen5 with built-in DMA, supporting both CCIX and CXL. Together with the Vitis™ unified software platform and Vivado® Design Suite, the Versal Premium series offers a complete solution stack for hardware and software developers for maximum productivity.
Greatly increased network traffic from 5G network rollout is driving demand for power-optimized throughput and compute density within the existing footprint and power envelopes. The Versal Premium series addresses these challenges by delivering up to 9Tb/s of scalable, adaptable serial bandwidth. This is achieved by utilizing 112G PAM4 transceivers and integrated connectivity for core, metro and data center interconnect (DCI) infrastructure that doubles bandwidth density per port and reduce latency by up to 50 percent.
The pre-engineered connectivity enables secure, multi-terabit Ethernet with the flexibility to support a variety of data rates and protocols. Channelized Ethernet cores deliver up to 5Tb/s of throughput in a minimized footprint and high-speed cryptography engines provide up to 1.6Tb/s of encrypted line-rate throughput and support for AES-GCM-256/128, MACsec, and IPsec.
The Versal Premium series will begin sampling with early access customers in the first half of 2021. Documention is currently available and customers can start prototyping now with the Versal Prime Evaluation Kit. Versal Prime devices implement many of the same architectural blocks as Versal Premium devices and support pin migration to Versal Premium.
Xilinx, Inc. announced the expansion of its automotive-qualified 16 nanometer (nm) family with two new devices – the Xilinx Automotive (XA) Zynq UltraScale+ MPSoC 7EV and 11EG. These two new parts deliver the highest programmable capacity, performance and I/O capabilities enabling high-speed, data aggregation, pre-processing, and distribution (DAPD), as well as compute acceleration for L2+ to L4 advanced driver-assistance systems (ADAS) and autonomous driving (AD) applications.
The new XA Zynq UltraScale+ MPSoC 7EV and 11EG devices were developed as a result of customer demand. The devices offer over 650,000 programmable logic cells – and nearly 3,000 DSP slices, which is 2.5X increase versus the previous largest device. In addition, the XA 7EV contains a video codec unit for h.264/h.265 encode and decode, while the XA 11EG includes 32 12.5Gb/s transceivers and provides four PCIe Gen3x16 blocks. The addition of these high-performance devices to the XA portfolio enables carmakers, robotaxi developers, and Tier-1 suppliers to perform the DAPD and compute acceleration in a power envelope that allows for scalable production deployments for AD vehicles.
The XA Zynq UltraScale+ MPSoC portfolio is qualified according to AEC-Q100 test specifications and integrates both Xilinx programmable logic and a feature-rich 64-bit quad-core Arm Cortex-A53 and dual-core Arm Cortex-R5 based processing system that is certified to ASIL-C level in the low power domain. The combination of these features, paired with the high data throughput capability of the new devices, accelerate the deployment of autonomous vehicles on the road today. To date, Xilinx has shipped more than 67 million auto-qualified solutions for ADAS systems and AD production vehicles to over 200 automotive companies including global Tier-1 suppliers, OEMs and start-ups.
The new XA Zynq UltraScale+ MPSoC devices are available for order today. Full technical details on the XA family can be found here. All XA devices are supported by Vitis and Vitis AI, the company’s new unified software platform that enables a broad range of developers to take advantage of the power of hardware adaptability.
element14, an Avnet community, continues to make developing with programmable logic devices easier, quicker and more advantageous for its community of engineers with the launch of its Path II Programmable series, sponsored by Xilinx.
Building on the success of last year’s successful training series, Path II Programmable, the only program of its type in the industry, will once again provide five community members with guidance and advice from knowledgeable community members and product specialists from Xilinx and Avnet as they journey to become FPGA design engineers. Over the course of 6 weeks, the participants will blog about their journey to share their knowledge and development experience with fellow community members.
Path II Programmable leverages the Avnet Ultra96-V2 development board, an Arm-based, Xilinx Zynq UltraScale+™ MPSoC open-source board to develop software applications, hardware devices and kernel programming for operating systems. By using programmable logic to accelerate the development of deep learning and Artificial Intelligence (AI) algorithms, the low-cost Avnet Ultra96-V2 makes the power of programmable logic accessible for all types of engineers, enabling software developers to take advantage of the benefits of hardware acceleration.
“Our Path to Programmable initiative provides members with a unique opportunity for professional development while continuing to address misconceptions around the complexity of developing products with programmable logic devices,” said Dianne Kibbey, Global Head of Community and Social Media for the element14 Community. “The element14 Community is committed to supporting its members as they build projects, develop their skills and stay up to date with the latest technologies. And by using the Ultra96-V2 to complete their projects, participants will gain valuable experience for future development of AI and Internet of Things (IoT) applications.”
Xilinx, Inc. expanded its Alveo data center accelerator card portfolio with the launch of the Alveo U50. The U50 card is the industry’s first low profile adaptable accelerator with PCIe Gen 4 support, uniquely designed to supercharge a broad range of critical compute, network and storage workloads, all on one reconfigurable platform.
The Alveo U50 provides customers with a programmable low profile and low-power accelerator platform built for scale-out architectures and domain-specific acceleration of any server deployment, on-premise, in the cloud and at the edge. To meet the challenges of emerging dynamic workloads such as cloud microservices, Alveo U50 delivers between 10-20x improvements in throughput, latency and power efficiency. For accelerated networking and storage workloads, the U50 card helps developers identify and eliminate latency and data movement bottlenecks by moving compute closer to the data.
Powered by the Xilinx UltraScale+ architecture, the Alveo U50 card is the first in the Alveo portfolio to be packaged in a half-height, half-length form factor and low 75-Watt power envelope. The card features high-bandwidth memory (HBM2), 100 gigabit per second (100 Gbps) networking connectivity, and support for the PCIe Gen 4 and CCIX interconnects. By fitting into standard PCIe server slots and using one-third the power, the Alveo U50 significantly expands the scope in which adaptable acceleration can be deployed to unlock dramatic throughput and latency improvements for demanding compute, network and storage workloads. The 8GB of HBM2 delivers over 400 Gbps data transfer speeds and the QSFP ports provide up to 100 Gbps network connectivity. The high-speed networking I/O also supports advanced applications like NVMe-oF™ solutions (NVM Express over Fabrics™), disaggregated computational storage and specialized financial services applications.
From machine learning inference, video transcoding and data analytics to computational storage, electronic trading and financial risk modeling, the Alveo U50 brings programmability, flexibility, and high throughput and low latency performance advantages to any server deployment. Unlike fixed architecture alternatives, the software and hardware programmability of the Alveo U50 allows customers to meet ever-changing demands and optimize application performance as workloads and algorithms continue to evolve.
Alveo U50 accelerated solutions deliver significant customer value across a range of applications, including:
- Deep learning inference acceleration (speech translation): delivers up to 25x lower latency, 10x higher throughput and significantly improved power efficiency per node compared to GPU-only for speech translation performance1;
- Data analytics acceleration (database query): running the TPC-H Query benchmark, Alveo U50 delivers 4x higher throughput per hour and reduced operational costs by 3x compared to in-memory CPU2;
- Computational storage acceleration (compression): delivers 20x more compression/decompression throughput, faster Hadoop and big data analytics, and over 30 percent lower cost per node compared to CPU-only nodes3;
- Network acceleration (electronic trading): delivers 20x lower latency and sub-500ns trading time compared to CPU-only latency of 10us4;
- Financial modeling (grid computing): running the Monte Carlo simulation, Alveo U50 delivers 7x greater power efficiency compared to GPU-only performance5 for a faster time to insight, deterministic latency and reduced operational costs.
The Alveo U50 is sampling now with OEM system qualifications in process. General availability is slated for fall 2019.
In order to provide more flexibility in how to use safety microcontrollers in automotive and industrial applications, Infineon Technologies AG cooperates with Xilinx Inc. and Xylon, d.o.o.. At the Embedded World trade fair 2019, they present a new Xylon IP core called logiHSSL. It enables high-speed communication between Infineon’s AURIX TC2xx and TC3xx microcontrollers and Xilinx’ SoC, MPSoC and FPGA devices via the Infineon High Speed Serial Link (HSSL). This serial link supports baudrates of up to 320 Mbaud at a net payload data-rate of up to 84%.
The HSSL is an Infineon native interface, low-cost in regards to pin-count as it requires only five pins – two LVDS with two pins each and one clk pin. So far, the HSSL interface is used to exchange data between AURIX devices and customer ASICs for performance or functional extension. Now, the new IP core will allow system developers to combine safety and security provided by AURIX with the wide range of functional possibilities brought to the table by the Xilinx devices. Linked devices can access and control each other’s internal and connected resources through the HSSL.
“Our AURIX microcontrollers are the market reference for many safety-critical applications, for example in advanced driver assistance and automated driving,” said Ralf Koedel, Marketing Director Microcontrollers at Infineon. “Now, we are creating new options for our customers in emerging applications that are both performance-hungry and safety-critical. Besides the ones mentioned these include for example industrial automation applications.”
“Our products are adopted in ADAS and AD architectures for data aggregation, pre-processing, and distribution as well as compute acceleration,” said Paul Zoratti, director Automotive Solutions, Xilinx. “Coupled with the AURIX family providing ASIL D level functional safety, this has created a strong market pull for an FPGA-based HSSL solution. Xylon’s licensable IP core will enable customers to implement a reliable HSSL communications path between Xilinx and Infineon devices without expending valuable development resources.”
To support development activities the partners are offering a starter kit. It includes a Xilinx evaluation kit, an Infineon AURIX evaluation board and a Xylon FMC board. Kit deliverables include the reference design with the test software application, Xylon’s logicBRICKS evaluation licenses, documentation and technical support.
At the Embedded World trade fair 2019 Infineon (booth #231, hall 3A) and its distribution partner EBV (booth #229, hall 3A) will show demo boards.
Xilinx, Inc. today announced it has extended its Zynq UltraScale+ Radio Frequency (RF) System-on-Chip (SoC) portfolio with greater RF performance and scalability. Building on the multi-market success of the Zynq UltraScale+ RFSoC base portfolio, next-generation devices can cover the entire sub-6 gigahertz (GHz) spectrum, which is a critical need for next-generation 5G deployment. They support direct RF sampling of up to 5 giga-samples per-second (GS/S) 14-bit analog-to-digital converters (ADCs) and 10 GS/S 14-bit digital-to-analog converters (DACs), both up to 6 GHz of analog bandwidth.
Xilinx’s RFSoC portfolio is the only single-chip adaptable radio platform that is designed to address current and future industry requirements. The portfolio now includes:
- Xilinx Zynq UltraScale+ RFSoC Gen 2: Sampling now with production scheduled for June 2019, this device meets regional deployment timelines in Asia and supports 5G New Radio.
- Xilinx Zynq UltraScale+ RFSoC Gen 3: Provides full sub-6GHz direct-RF support, extended millimeter wave interface, and up to 20 percent power reduction in the RF data converter subsystem compared to the base portfolio. The product will be available in 2H 2019.
The new products monolithically integrate higher-performance RF data converters that deliver the broad spectrum coverage required for the deployment of 5G wireless communications systems, cable access, advanced phased-array radar solutions and additional applications including test & measurement and satellite communications. By eliminating discrete components, the devices enable up to a 50 percent power and footprint reduction, making them ideal for the needs of telecommunications operators seeking to enable massive multiple-input, multiple-output base stations for their 5G systems.”
With pin-compatibility across the portfolio, customers can design and deploy their systems now using first-generation devices with a roadmap to Gen 2 and Gen 3 for greater performance. More information on Zynq UltraScale+ RFSoCs, including details of the ZCU111 Evaluation Kit, can be found at www.xilinx.com/rfsoc.
Xilinx, Inc. announced that it has introduced a complete HDMI 2.1 IP subsystem to its portfolio of intellectual property cores, enabling Xilinx devices to transmit, receive and process up to 8K (7680 x 4320 pixels) ultra-high-definition (UHD) video in pro AV equipment, including cameras, streaming media players, professional monitors, LED walls, projectors and KVM, as well as broadcast products such as end points and infrastructure that are being upgraded to handle 8K video.
Customers are increasingly adopting machine learning to monetize and improve workflows in diverse applications such as broadcast, pro AV, automotive and surveillance. HDMI 2.1 data rates are provided by Xilinx’s highly reliable high-speed I/O transceivers. This, combined with native 8K interfaces supported by HDMI 2.1 now make it possible to replace several ASSP’s or fixed-function products support processing, compression, high-quality analytics and decision-making with a single Xilinx device.
Xilinx will demonstrate the HDMI 2.1 IP subsystem alongside a range of other cores for compression, video processing and digital-signage analytics at booth 15-D240, ISE Integrated Systems Europe, RAI Amsterdam, February 5-8.
Xilinx, Inc. announced that its Zynq UltraScale+ MPSoC family has been assessed as SIL 3, HFT1 capable, according the IEC 61508 functional-safety specification, by Exida, the leading functional safety certification agency. This assessment means product developers can build new high-performing systems including artificial intelligence (AI) for safety-critical applications using Xilinx’s feature-rich, highly integrated single-chip MPSoC family, with the assurance of IEC 61508 functional-safety certification up to Safety Integrity Level 3 (SIL 3).
“AI-based systems need to be safe systems,” said Yousef Khalilollahi, vice president, core vertical markets, Xilinx. “Today’s announcement underscores our leadership in this new category of devices, further raising performance and extending design flexibility. Zynq UltraScale+ MPSoC was designed with safety and security in mind and is the ideal architecture to support industrial IoT or Industrie 4.0 platforms and future generations of automotive, aviation, and AI-based systems.”
The independent assessment of the Zynq UltraScale+ MPSoC family is a significant milestone in Xilinx’s functional safety offerings. The achievement built upon the industry’s first commercial ARM-based SoC, the Zynq-7000, able to demonstrate compliance to functional safety requirements for on-chip redundancy (HFT=1). Both device families leverage Xilinx’s competencies in implementing isolated function domains on a single die with hardware protection mechanisms, creating the required hardware fault tolerance consistent with on-chip redundancy (HFT=1). In addition, developers can take advantage of the embedded FPGA fabric to accelerate performance beyond conventional software-based systems and thus achieve the fast response times and low latency typically required of safety-critical systems. Xilinx has also introduced safety-enhanced automotive-
Developers can find tools and resources to support highly integrated safety-critical systems design by purchasing access to Xilinx’s online Functional Safety Lounge. Privileges include access to the Safety Manual for Zynq UltraScale+ MPSoC, device and architecture updates, tool-flows and documentation including future reports and assessments.