The secure boot protects devices from unauthorized modification by verifying the authenticity of the boot code. Its importance is growing as society digitalizes and the number of devices on the Internet of Things (IoT) soars. A secure boot prevents an adversary from compromising device operation. This article reviews the basic elements of secure boot processes, […]
How are AI and ML used for advanced threat detection?
The increasing number of threat vectors and the growing size of the attack surface in today’s communication and computer networks demand more powerful and faster threat detection. Legacy tools are no longer adequate. To ensure cybersecurity, high-speed threat detection based on artificial intelligence (AI) and machine learning (ML) is increasingly being deployed. This article reviews […]
How is Zephyr used for edge AI and sensors?
Zephyr is a scalable open-source real-time operating system (RTOS) hosted by the Internet of Things (IoT) and embedded technology section of the Linux Foundation. Its modular architecture makes it highly flexible and suitable for resource-constrained edge devices and sensors. This article reviews Zephyr’s structure and features, examines how Zephyr supports neural networks, and discusses how […]
How do AI and ML enhance SASE security?
Secure Access Service Edge (SASE) has emerged as a leading architecture for cloud deployments. Its primary function is to provide comprehensive cloud-based secure access while maintaining seamless access to data and applications for users of cloud computing services. This article compares SASE with a traditional network architecture and then looks at how artificial intelligence (AI) […]
How is HIL testing used for onboard EV chargers?
Hardware-in-the-loop (HIL) testing is a real-time simulation that enables designers to test embedded code for EV chargers without needing the actual system hardware. It speeds development efforts and reduces development costs. This article begins with an overview of HIL testing and onboard chargers (OBCs), looks at specific types of HIL testing applied to OBCs, and […]
How does a recurrent neural network (RNN) remember?
There are several types of neural networks (NNs). Recurrent NNs (RNNs) can “remember” data and use past information for inferences. This article compares recurrent NNs with feed-forward NNs (FFNNs) that can’t remember, then digs into the concept of backpropagation through time (BPTT) and closes by looking at long short-term memory (LSTM) RNNs. RNNs and FFNNs […]
What’s the difference between GPUs and TPUs for AI processing?
Graphic processing units (GPUs) and tensor processing units (TPUs) are specialized ICs that support different types of artificial intelligence (AI) and machine learning (ML) algorithms. This article begins with a brief overview of tensors and where they fit into the mathematics of AI and ML; it then looks at the different structures of GPUs and […]
What are the challenges when testing chiplets?
Chiplet testing begins with performance simulations during the design process. Compared with monolithic devices, heterogeneous chiplets require more complex testing, including known good die (KGD) testing, final test, and system level test. Success also depends on the implementation of design for test (DfT) based on several IEEE standards. Chiplet designers need high-speed tools that can […]
How can in-package optical interconnects enhance chiplet generative AI performance?
Generative artificial intelligence (AI) requires rapid and continuous movement of large amounts of data. In a growing number of instances, electrical input/output (I/O) connections between the ICs in chiplets are becoming a bottleneck to higher performance. Key electrical I/O performance barriers include power efficiency, bandwidth, and latency. This FAQ looks at the anticipated benefits of […]
How do UCIe and BoW interconnects support generative AI on chiplets?
The bunch-of-wires (BoW) and Universal Chiplet Interconnect Express (UCIe) standards provide designers with tradeoffs in terms of throughput, interconnect density, delay, and bump pitch. This FAQ compares the performance of BoW and UCIe and looks at how optical interconnects may provide a path to even higher performance interconnects in chiplets. To realize optimal performance for […]
