Secure Access Service Edge (SASE) has emerged as a leading architecture for cloud deployments. Its primary function is to provide comprehensive cloud-based secure access while maintaining seamless access to data and applications for users of cloud computing services. This article compares SASE with a traditional network architecture and then looks at how artificial intelligence (AI) […]
FAQ
How is HIL testing used for onboard EV chargers?
Hardware-in-the-loop (HIL) testing is a real-time simulation that enables designers to test embedded code for EV chargers without needing the actual system hardware. It speeds development efforts and reduces development costs. This article begins with an overview of HIL testing and onboard chargers (OBCs), looks at specific types of HIL testing applied to OBCs, and […]
How does a recurrent neural network (RNN) remember?
There are several types of neural networks (NNs). Recurrent NNs (RNNs) can “remember” data and use past information for inferences. This article compares recurrent NNs with feed-forward NNs (FFNNs) that can’t remember, then digs into the concept of backpropagation through time (BPTT) and closes by looking at long short-term memory (LSTM) RNNs. RNNs and FFNNs […]
What’s the difference between GPUs and TPUs for AI processing?
Graphic processing units (GPUs) and tensor processing units (TPUs) are specialized ICs that support different types of artificial intelligence (AI) and machine learning (ML) algorithms. This article begins with a brief overview of tensors and where they fit into the mathematics of AI and ML; it then looks at the different structures of GPUs and […]
What are the programming essentials for LoRa nodes?
LoRa (long-range) technology ensures reliable long-range communication between a node and gateway, making it well-suited for a range of Internet-of-Things (IoT) applications. The purpose of building a LoRa node is to reduce costs while ensuring long-term, low-power use for devices. LoRa’s low power is affected by several features, covered below. Features Smart programming. The written […]
Build a 5G Open RAN test lab with open-source software tools
Open-source software provides network components that you can use to simulate 5G network functions from the network core to the radio. Developing and deploying a laboratory infrastructure to support testing 5G and open radio-access network (Open RAN) systems can present a daunting and complex task. Prior to Open RAN, this task was only possible by…
Flexible PTP profiles ease the transition to 5G
5G brought architecture changes that require synchronization. Depending on the location and network site, those timing requirements require different PTP profiles and PTP capacity.
What are the challenges when testing chiplets?
Chiplet testing begins with performance simulations during the design process. Compared with monolithic devices, heterogeneous chiplets require more complex testing, including known good die (KGD) testing, final test, and system level test. Success also depends on the implementation of design for test (DfT) based on several IEEE standards. Chiplet designers need high-speed tools that can […]
How can in-package optical interconnects enhance chiplet generative AI performance?
Generative artificial intelligence (AI) requires rapid and continuous movement of large amounts of data. In a growing number of instances, electrical input/output (I/O) connections between the ICs in chiplets are becoming a bottleneck to higher performance. Key electrical I/O performance barriers include power efficiency, bandwidth, and latency. This FAQ looks at the anticipated benefits of […]
How do UCIe and BoW interconnects support generative AI on chiplets?
The bunch-of-wires (BoW) and Universal Chiplet Interconnect Express (UCIe) standards provide designers with tradeoffs in terms of throughput, interconnect density, delay, and bump pitch. This FAQ compares the performance of BoW and UCIe and looks at how optical interconnects may provide a path to even higher performance interconnects in chiplets. To realize optimal performance for […]
