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Hardware-software platform helps develop/debug ARC EM-based SoCs

January 25, 2019 By Aimee Kalnoskas Leave a Comment

Synopsys, Inc. announced the new tform to accelerate software development and debug of ARC EM processor-based system-on-chips (SoC) for a wide range of ultra-low power embedded applications such as IoT, sensor fusion, and voice applications. The ARC EM Software Development Platform includes an FPGA-based hardware board with commonly used peripherals and downloadable platform packages. The Development Platform is supported by Synopsys’ MetaWare Development Tool Kit, which includes a compiler, debugger, and libraries optimized for maximum performance with minimal code size. In addition, the embARC Open Software Platform gives developers online access to device drivers, examples, and a suite of free and open-source software that enables them to speed software development for their ARC-based embedded systems.

The ARC EM Software Development platform supports all ARC EM processor families and EM-based subsystems. To facilitate development of ARC processor-based designs, the platform includes several debug and trace interfaces as well as a range of on-board peripherals including motion sensors, flash memory, Bluetooth, and Wi-Fi used in IoT edge devices. The ARC EM Software Development Platform provides extensibility using Arduino UNO revision 3 compatible shields, Digilent Pmod modules, and mikroBUS add-on boards. For greater flexibility, a memory-mapped External Bus Interface (EBI) is also available to control any memory-mapped peripherals located on an external custom board over a generic pin header.

The ARC EM Software Development Platform is supported by a robust ecosystem of development tools and software, including the MetaWare Development Toolkit, which enables the development and debugging of highly optimized code. In addition, Synopsys’ embARC Open Software Platform gives software developers online access to a comprehensive suite of free and open-source software, such as device drivers, FreeRTOS, IoT middleware, and examples, that eases the development IoT, sensor, and voice applications. The software in the embARC Open Software Platform includes popular protocols used in IoT devices and networking stacks, such as lwip, and commonly used security protocols, such as mbedTLS. The latest version of the embARC Open Software Platform also supports the OpenThread protocol, an open-source implementation of the Thread networking protocol released by Nest Labs, Inc.

The DesignWare ARC EM Software Development Platform is available now from Trenz.

Static analysis technology updated with security for enterprise applications

January 16, 2019 By Aimee Kalnoskas Leave a Comment

Synopsys, Inc. announced the availability of a new version of its Coverity static application security testing (SAST) solution, which enables organizations to build secure applications faster. The latest release of Coverity addresses three increasingly important needs for enterprise application security teams: scalability, broad language and framework support, and comprehensive vulnerability analysis.

Coverity enables enterprise organizations to scale their SAST efforts across large application portfolios. The latest Coverity solution now includes a feature called ‘analysis without build’ that allows security teams to onboard and analyze thousands of applications quickly and easily. Security teams can now simply point Coverity to a source code project and begin analyzing in seconds, without first having to do a full build operation for each application. Unlike other SAST solutions, Coverity automatically detects project types and fetches the dependencies that would normally be incorporated in the build process. Use of this new feature ensures comprehensive analysis and eliminates the need to manually declare dependencies.

The ecosystem of programming languages and frameworks used to build applications is expanding, and SAST tools need to understand how each one works in order to be effective. To address the needs of enterprise organizations with diverse application portfolios, Synopsys has significantly expanded Coverity’s language and framework coverage. The latest Coverity release introduces support for TypeScript, .NET Core, Swift 4.1, and Ruby on Rails, as well as more than 50 different frameworks for Java, JavaScript, C#, including Angular, React, and Vue.

The Coverity analysis engine utilizes a variety of techniques to look at code in different ways and find the most actionable and critical security vulnerabilities. In response to the growing popularity of frameworks, the latest Coverity release includes dramatically improved framework analysis, which allows customers to more accurately detect client-side and back-end web services vulnerabilities. Coverity can also now analyze JavaScript framework templates, which are a popular means of client-side data binding. Coverity can now scan the HTML generated on the fly from such templates to find additional cross-site scripting vulnerabilities.

RTL to GDSII compiler delivers 20% better QoR, 2X faster time-to-results

November 7, 2018 By Aimee Kalnoskas Leave a Comment

Synopsys has unveiled Fusion Compiler, an innovative RTL-to-GDSII product that enables a new era in digital design implementation. By fusing a novel high-capacity synthesis technology with the IC Compiler II industry-leading place-and-route technology, Fusion Compiler offers new levels of predictable quality-of-results (QoR) to address the challenges presented by the industry’s most advanced designs. This unified architecture shares technologies across the RTL-to-GDSII flow to enable a highly convergent system delivering 20 percent better QoR and 2X faster time-to-results (TTR).

Fusion Compiler is tapeout-validated at market-leading semiconductor companies and has been proven to deliver the highest-quality designs. Fusion Compiler also enables a single cockpit for RTL-to-GDSII implementation, enabling unparalleled levels of design productivity, flexibility, and throughput to maximize power, performance, and area (PPA) for the most challenging designs.

“Enablement of the next generation of market-shaping products has demanded the reassessment of how design productivity and quality-of-results can be improved,” said Sassine Ghazi, co-general manager of the Design Group at Synopsys. “Leveraging the leading technologies from IC Compiler II and fusing novel, high-capacity synthesis and our industry-leading golden signoff technologies onto the same scalable data model, Fusion Compiler is engineered to offer the best QoR in the shortest time.”

Fusion Compiler is built on a single, highly-scalable data model that supports common signoff analysis, optimization, concurrent clock data optimization, clock topology creation, and routing engines. These best-in-class engines form a single unified optimization framework that is central to Fusion Compiler’s predictable flow. Its architecture also enables sharing of advanced technologies across the RTL-to-GDSII design flow. Technologies previously used only in place-and-route can now be applied during synthesis, and vice versa, enabling new levels of timing, power, and area.

IC design software includes DFT circuit modifications to reduce silicon test costs

October 30, 2018 By Aimee Kalnoskas Leave a Comment

Synopsys announced the availability of Test Fusion technology with new test point functionality, providing design teams with powerful design-for-test (DFT) circuit modifications to reduce silicon test costs by an average of forty percent and increase defect detection while meeting design targets for power, performance, and area. Test Fusion ensures the test points avoid introducing routing congestion and minimize area impact, in contrast to traditional test point implementation techniques. RTL designers can easily deploy test points with a single step that automatically combines Synopsys’ SpyGlass DFT ADV testability analysis, DFTMAX design-for-test, and Synopsys synthesis products, then run TetraMAX II automatic test pattern generation (ATPG) to create efficient silicon manufacturing tests. The solution is fully certified to comply with the ISO 26262 automotive functional safety standard and is widely deployed among semiconductor manufacturers.

To meet lower cost and increasing quality requirements, semiconductor manufacturers seek new technologies to improve detecting defective silicon prior to shipment. Several industry segments, such as automotive, are challenged to meet manufacturing test cost goals while achieving quality levels for their integrated circuits (ICs) of less than one defective part per million. Synopsys test points assist meeting these requirements by modifying the design to improve the ability of TetraMAX II to generate silicon test programs. SpyGlass DFT ADV analyzes designs and determines the most optimal and effective locations for test points that both decrease test pattern volume and increase defect coverage. Test Fusion technology ensures DFTMAX and Synopsys synthesis tools work in combination to implement the test points at the selected locations while minimizing routing using physical design data. Furthermore, Test Fusion provides an unprecedented reduction of area and congestion by enabling multiple test points to share a single test register based on physical proximity.

For more information on the comprehensive Synopsys Test solution, visit www.synopsys.com/test.

IC design software gets better Spice circuit simulation for analog/mixed-signal work

October 25, 2018 By Aimee Kalnoskas Leave a Comment

Synopsys announced that its Custom Design Platform has been enhanced with innovative new FineSim SPICE circuit simulation and Custom Compiler custom layout technologies to address the growing needs of accelerating robust analog/mixed-signal (AMS) designs at advanced process nodes and high-reliability applications. The new analog simulation technologies in the latest FineSim SPICE release provide 3X faster performance for large post-layout circuits and adds new RF-class analysis capabilities.

The 2018.09 release of Custom Compiler provides new Extraction Fusion technology with StarRC parasitic extraction and DRC Fusion technology with IC Validator signoff physical verification that enable tighter design/layout collaboration and fewer late-stage design iterations. Combined with enhancements in Custom Compiler’s visually-assisted automation technology, the Synopsys Custom Design Platform delivers new levels of design and layout productivity to accelerate AMS design.

Seagate and other industry leaders highlighted their experiences in achieving significant productivity gains by adopting the Synopsys Custom Design Platform at the 2018 Design Automation Conference (DAC). Videos of these presentations are available on the Synopsys web site.

The Synopsys Custom Design Platform is a unified suite of design and verification tools that accelerates the development of robust custom and AMS designs. Anchored by the Custom Compiler custom design environment, the platform features industry-leading circuit simulation performance, a fast, easy-to-use custom layout editor complemented with best-in-class technologies for parasitic extraction, reliability analysis, and physical verification.

Key features of the Custom Design Platform include reliability-aware verification, visually-assisted layout, and Extraction Fusion and DRC Fusion technologies. Reliability-aware verification ensures robust AMS design with signoff-accurate transistor-level EM/IR analysis, large-scale Monte Carlo simulation, aging analysis, and other verification checks. Visually-assisted automation is a pioneering approach to reducing layout effort, especially for advanced-node designs, that is proven to deliver 2-10X higher productivity. Extraction Fusion and DRC Fusion technologies shorten time to design closure and reduce late iterations.

DDR5 and LPDDR5 design IP said to be most power-efficient yet

October 25, 2018 By Aimee Kalnoskas Leave a Comment

Synopsys has announced new DesignWare Memory Interface IP solutions supporting the next-generation DDR5 and LPDDR5 SDRAMs. The DDR5 and LPDDR5 IP significantly increase memory interface bandwidth compared to DDR4 and LPDDR4 SDRAM interfaces, while reducing area and improving power efficiency.

The DesignWare DDR5 IP, operating at up to 4800 Mbps data rates, can interface with multiple DIMMs per channel up to 80 bits wide, delivering the fastest DDR memory interface solution for artificial intelligence (AI) and data center system-on-chips (SoCs). The industry’s first LPDDR5 IP, running at up to 6400 Mbps, provides significant area and power savings for mobile and automotive SoCs with its dual-channel memory interface option that shares common circuitry between independent channels. For additional power savings, the DesignWare Memory Interface IP solutions provide several low-power states with short exit latencies, and offer multiple pre-trained states for dynamic frequency change capability. The DDR5 and LPDDR5 controller and PHY seamlessly interoperate via the latest DFI 5.0 interface, providing a complete memory interface IP solution for high-bandwidth, low-power SoC designs.

The DesignWare DDR5 and LPDDR5 IP solutions support all required features of the DDR and LPDDR specifications, enabling designers to incorporate the necessary functionality into their SoCs:

Firmware-based training via an embedded calibration processor in the PHY optimizes the boot-time memory training for highest data reliability and margin at the system level. It also allows fast updates to the training algorithms without requiring changes to the hardware
Decision feedback equalization (DFE) used in the input receivers reduces the impact of intersymbol interference (ISI) to improve signal integrity
Reliability, availability, serviceability (RAS) features, including inline or sideband error correcting code (ECC), parity, and data cyclic redundancy checks (CRC), reduce system downtime
Synopsys PHY hardening and signal/power integrity expertise enable faster design completion time and a higher degree of design confidence
Synopsys VIP for DDR5 and LPDDR5 provides randomized configuration and runtime selection, as well as built-in comprehensive coverage, verification plan, and protocol checks for increased productivity”

The DesignWare DDR5 PHY and LPDDR5 PHY are scheduled to be available in Q1 of 2019, the DesignWare DDR5 Controller and LPDDR5 Controller are scheduled to be available in Q2 of 2019, and the VC Verification IP for DDR5 and LPDDR5 is available now.

Software helps explore processing and memory architecture options for AI SoCs

October 16, 2018 By Aimee Kalnoskas Leave a Comment

Synopsys, Inc. announced the availability of its next-generation architecture exploration, analysis, and design solution, Platform Architect Ultra, to address the system challenges of artificial intelligence (AI)-enabled system-on-chips (SoCs). Architects of neural network enabled SoCs need to carefully balance the required convolutional neural network (CNN) throughput against the available power and performance budget that data center or embedded devices can sustain. Platform Architect Ultra flexibly maps CNN algorithms and workloads to explore processing and memory architecture options, enabling architects to analyze, select, optimize, and tune algorithms and architectures for performance and power requirements.

Synopsys’ Platform Architect Ultra, developed in collaboration with AI SoC leaders, is the next-generation release of Platform Architect, embedding the latest technology to efficiently perform dynamic simulation of multicore architectures. Platform Architect Ultra introduces SMART Tables for context-sensitive data entry and error checking, and SMART Charts for visual root-cause sensitivity analysis of candidate architectures. It also introduces a hierarchical design concept for fast creation and packaging of a design, including ready-to-map workloads, architecture models, and AI reference system, including CNN frameworks such as Caffe and TensorFlow, enabling architects to quickly analyze and optimize a proposed architecture design.

“Through our collaboration with leading AI SoC companies, we know that architecture teams must carefully balance power, performance, and programmability to succeed in this highly competitive market,” said Eshel Haritan, vice president of R&D in the Synopsys Verification Group. “Platform Architect Ultra’s parallelized exploration, performance, and power optimization capabilities allow designers of neural network architectures and algorithms to quickly find a balanced architecture and eliminate late changes in SoC design.”

Cloud-based IC design environment includes TSMC design infrastructure, process technology

October 4, 2018 By Aimee Kalnoskas Leave a Comment

Synopsys, Inc. announced it has collaborated with TSMC and leading cloud providers Amazon Web Services (AWS) and Microsoft Azure, to provide a streamlined cloud-based IC design environment on the Synopsys Cloud Solution. The Synopsys Cloud Solution provides optimized, secure infrastructure and services to enable IC design and verification teams to take full advantage of the benefits of the cloud. Built for unique EDA workloads, the Synopsys Cloud Solution supports compute infrastructures from major public cloud providers, as well as Synopsys-hosted infrastructures. Through collaboration with TSMC, the Synopsys Cloud Solution enables system-on-chip (SoC) teams to design securely and effectively in the cloud using Synopsys EDA tools and IP, third-party IP from Arm, and TSMC design infrastructure collateral, including process technology files, process design kits (PDKs), and foundation IP.

The Synopsys Cloud Solution provides access to cloud-ready Synopsys design and verification platforms, reference flows, and a cloud-based license server. Complementing the design and verification platforms, the Lynx Design System provides powerful, easy-to-use automation for cloud-based SoC design. The environment enables designers to take advantage of cloud scaling for peak usage and full-flow workloads.

Leveraging the massive scaling offered by Synopsys tools like PrimeTime signoff; StarRC extraction; IC Validator signoff physical verification; HSPICE, CustomSim, and FineSim circuit simulation; SiliconSmart characterization; VCS functional verification; VC Formal formal verification; and Z01X fault simulation, the Synopsys Cloud Solution provides a robust environment to accelerate project cycle times. Synopsys will demonstrate these benefits at the TSMC OIP Forum [booth #716] on October 3, 2018, in Santa Clara, CA.

As the leading provider of interface IP for high-performance cloud computing SoCs, Synopsys continuously strives to accelerate design cycle times to meet customers’ demanding schedules. By leveraging the performance of the IC Validator signoff physical verification solution with the scalability of the cloud to thousands of CPU cores, Synopsys’ IP group successfully taped out the high-speed DesignWare PHY IP for PCI Express 5.0 on TSMC’s advanced 7-nm process and met their aggressive project timeline.

“Arm’s partners are increasingly turning to cloud computing, and we are enabling them to use Arm IP with trusted cloud service providers like Amazon Web Services and Microsoft Azure to help them achieve their time-to-market goals,” said Rene Haas, president, Arm IP Products Group. “We’ve collaborated with Synopsys to enable our partners to take advantage of the Synopsys Cloud Solution for TSMC using Synopsys design and verification tools, along with cloud-proven QuickStart Implementation Kits for Arm’s leading-edge, high-performance cores, including our recently announced Cortex-A76.”

The Synopsys Cloud Solution provides optimized, secure infrastructure and services to enable IC design and verification teams to take full advantage of the benefits of the cloud. Built for unique EDA workloads, the Synopsys Cloud Solution supports compute infrastructures from major public cloud providers, as well as Synopsys-hosted infrastructures.

The Synopsys Cloud Solution includes:

Support for complete EDA design flows, including cloud-optimized products that exploit the scalability of cloud infrastructures
A range of services for EDA environments in the cloud, such as setup, configuration, on-boarding, tools, and license installation to provide fully integrated tools to handle diverse/complex EDA workflows
Synopsys ZeBu® Cloud services, providing access to the industry’s fastest emulation system in a fully managed cloud-based model.

Synopsys has been hosting customers in the cloud for more than 15 years. Our expanded Synopsys Cloud Solution leverages our deep understanding of EDA-specific requirements to accelerate adoption of the cloud for IC design and verification. For more information on the Synopsys Cloud Solution, visit www.synopsys.com/cloud.

SoC design software runs analysis of peak power use

June 22, 2018 By Jillian Zavoda Leave a Comment

Synopsys, Inc. today introduced PrimePower, an expanded power analysis solution created to accelerate system-on-chip (SoC) design closure by extending signoff power analysis to drive early design implementation and accurate reliability analysis. Revolutionary technologies based on Synopsys’ golden PrimeTime static timing analysis and signoff empower designers to perform faster and uniquely accurate power analysis and power-driven optimizations earlier in the implementation phase with RTL simulation vectors. PrimePower’s native interface with Synopsys’ ZeBu emulation system provides a comprehensive system-level-to-signoff power analysis solution, enabling designers to efficiently and accurately pinpoint and fix power and reliability issues to achieve robust design closure.

Reliability has emerged as a critical requirement in advanced-node designs, where aggressive transistor scaling, decreased voltage margins, and increased power have made reliability analysis a much more significant issue in design. PrimePower addresses the increased reliability concerns at sub-7-nanometer (nm) nodes by expanding power and reliability signoff and engineering change order (ECO) closure capabilities from physical awareness to cell electromigration (EM) effects. PrimePower’s native integration with PrimeTime enables concurrent signoff timing, power, and reliability ECO for single-pass design closure. In addition, its timing and power interfaces enable efficient reliability signoff analysis and deliver robust SoC designs with improved endurance for high-intensive computing tasks throughout the design life cycle.

“HiSilicon builds AI-enabled SoCs on leading-edge semiconductor processes. These SoCs perform the most compute-intensive tasks throughout their service life,” said Huatao Yu, senior manager of worldwide physical design at HiSilicon. “PrimePower enabled advanced reliability modeling and unique signoff-driven auto-fixing in our design flow, saving us weeks of design iterations while enabling lifetime robustness for these intelligent chips.”

The new PrimePower solution strengthens the Synopsys Design Platform by not only enabling early RTL-based analysis and optimizations, but also providing a single DNA backbone for power analysis throughout the digital low-power design flow, from physical implementation to signoff. A key component of the recently announced Fusion Technology solution, PrimePower signoff technology in the Synopsys Design Platform delivers out-of-the-box perfect correlation and best-in-class design power quality of results (QoR) for enhanced SoC performance, power, and area (PPA) closure.

“Emerging technologies such as artificial intelligence, visual computing, and virtual reality are driving innovation for power and reliability of advanced chips,” said Michael Jackson, corporate vice president of marketing for the Design Group at Synopsys. “PrimePower connects signoff power and reliability-driven design optimization with system emulation, augmenting Synopsys’ low-power design portfolio and enabling an efficient path to robust chip designs that can endure real-world compute-intensive scenarios, such as AI self-driving or mobile-VR game play simulations.”