Hardware-in-the-loop (HIL) testing is a real-time simulation that enables designers to test embedded code for EV chargers without needing the actual system hardware. It speeds development efforts and reduces development costs. This article begins with an overview of HIL testing and onboard chargers (OBCs), looks at specific types of HIL testing applied to OBCs, and […]
Featured
How does a recurrent neural network (RNN) remember?
There are several types of neural networks (NNs). Recurrent NNs (RNNs) can “remember” data and use past information for inferences. This article compares recurrent NNs with feed-forward NNs (FFNNs) that can’t remember, then digs into the concept of backpropagation through time (BPTT) and closes by looking at long short-term memory (LSTM) RNNs. RNNs and FFNNs […]
EE Training Day: ADAS domain controllers and transition to central compute
ADAS domain controller trends bring more compute to the central ADAS ECU and reduce edge computing, leading to fully centralized compute modules in the next decade. This webinar covers the prevalent levels of autonomy today, how the new architectural trends align with increasing compute and autonomy features, and the impact of SW-defined vehicle trends in […]
What’s the difference between GPUs and TPUs for AI processing?
Graphic processing units (GPUs) and tensor processing units (TPUs) are specialized ICs that support different types of artificial intelligence (AI) and machine learning (ML) algorithms. This article begins with a brief overview of tensors and where they fit into the mathematics of AI and ML; it then looks at the different structures of GPUs and […]
What are the programming essentials for LoRa nodes?
LoRa (long-range) technology ensures reliable long-range communication between a node and gateway, making it well-suited for a range of Internet-of-Things (IoT) applications. The purpose of building a LoRa node is to reduce costs while ensuring long-term, low-power use for devices. LoRa’s low power is affected by several features, covered below. Features Smart programming. The written […]
What are the challenges when testing chiplets?
Chiplet testing begins with performance simulations during the design process. Compared with monolithic devices, heterogeneous chiplets require more complex testing, including known good die (KGD) testing, final test, and system level test. Success also depends on the implementation of design for test (DfT) based on several IEEE standards. Chiplet designers need high-speed tools that can […]
How can in-package optical interconnects enhance chiplet generative AI performance?
Generative artificial intelligence (AI) requires rapid and continuous movement of large amounts of data. In a growing number of instances, electrical input/output (I/O) connections between the ICs in chiplets are becoming a bottleneck to higher performance. Key electrical I/O performance barriers include power efficiency, bandwidth, and latency. This FAQ looks at the anticipated benefits of […]
How do UCIe and BoW interconnects support generative AI on chiplets?
The bunch-of-wires (BoW) and Universal Chiplet Interconnect Express (UCIe) standards provide designers with tradeoffs in terms of throughput, interconnect density, delay, and bump pitch. This FAQ compares the performance of BoW and UCIe and looks at how optical interconnects may provide a path to even higher performance interconnects in chiplets. To realize optimal performance for […]
What is the heterogeneous integration roadmap, and how does it support generative AI?
The heterogeneous integration roadmap (HIR) is an ongoing initiative of the IEEE Electronics Packaging Society. It’s a living document that continues to evolve and expand in response to technological developments like the growth of generative artificial intelligence (AI) and quantum computing. This FAQ starts with a brief overview of heterogeneous integration, looks at the scope […]
How does the open domain-specific architecture relate to chiplets and generative AI?
The Open Domain-Specific Architecture (ODSA) is a project within the Open Compute Project (OCP) community to establish open physical and logical die-to-die (D2D) interfaces for chiplets. The goal is to democratize the design and use of chiplets for domain-specific high-performance computing (HPC) applications like generative artificial intelligence (AI). Domain-specific architectures (DSAs) are an emerging approach […]
