Microchip Technology announces its portfolio of SAMA7D65 MPUs based on the Arm Cortex-A7 core running up to 1 GHz and offered in a System-in-Package (SiP) with a 2 Gb DDR3L and System-on-Chip (SoC). The SAMA7D65 MPU series is designed to target Human-Machine Interface (HMI) and connectivity applications with its advanced graphic features. The graphic features of the SAMA7D65 […]
Artificial intelligence/ML
Microcontroller achieves 168 µa/MHz power consumption
Renesas Electronics Corporation introduced the RA4L1 microcontroller (MCU) group, including 14 new devices with ultra-low power consumption, advanced security features, and segment LCD support. Based on an 80-MHz Arm Cortex M33 processor with TrustZone support, the new MCUs deliver an unmatched combination of performance, features, and power savings that enable designers to address a myriad […]
SoC adds computing and wireless to IoT designs
The Talaria 6 SoC from Innophase IoT combines an Arm MCU, Wi-Fi 6, Bluetooth Low Energy 6.0, and RF amps into a single package. IoT devices such as cameras, smoke alarms, environmental monitors, drones and audio devices increasingly need wireless connectivity. Innophase IoT has introduced the Talaria 6 family of SoCs improve on the company’s […]
Next generation chip architecture balances performance with battery life
Imagination Technologies announces the Imagination DXTP GPU IP, designed to accelerate graphics and compute workloads on smartphones and other power-constrained devices. The DXTP delivers 20% improved power efficiency (FPS/W) on graphics workloads compared to its DXT equivalent through micro-architectural improvements. The DXTP provides 64 GPixel/s, 2 TFLOPS FP32, and 8 TOPS INT8 in a compute […]
Display combines Pi compute with Clea OS
SECO S.p.A. and Raspberry Pi Ltd announce the presentation of the cutting-edge Human-Machine Interface (HMI) solution, the SECO Pi Vision 10.1 CM5 powered by Raspberry Pi Compute Module 5, at Embedded World 2025, the premier trade show for embedded technologies taking place from March 11-13 in Nuremberg, Germany. This new integrated solution underscores the companies’ shared […]
What are the different MLPerf benchmarks from MLCommons?
Formulated and managed by MLCommons, MLPerf benchmarks measure key operational parameters of artificial intelligence (AI) accelerators across multiple industries. These standardized metrics help semiconductor companies optimize performance and support the development of efficient AI chip designs. This article discusses MLPerf’s crucial role in facilitating comprehensive benchmark testing for tiny and edge computing systems while scaling […]
Memory stack design reaches 4 TB/s bandwidth with eight dies
Numem will be at the upcoming Chiplet Summit to showcase its high-performance solutions. By accelerating the delivery of data via new memory subsystem designs, Numem solutions are re-architecting the hierarchy of AI memory tiers to eliminate the bottlenecks that negatively impact power and performance. The rapid growth of AI workloads and AI Processor/GPUs are exacerbating the memory bottleneck […]
Chip design framework shows 2-3x efficiency for AI processing
Arm has released the first public specification of its Chiplet System Architecture (CSA), a framework for standardizing chipset connectivity and system partitioning. The specification is now supported by more than 60 technology companies, including ADTechnology, Alphawave Semi, AMI, Cadence, Jaguar Micro, Kalray, Rebellions, Siemens, and Synopsys. The CSA framework enables designers to create reusable chipsets […]
Accelerating high-performance AI workloads with photonic chips
Artificial intelligence (AI) and machine learning (ML) continue to push the limits of conventional semiconductor architectures. To increase speeds, lower latency, and optimize power consumption for high-performance workloads, semiconductor companies and research institutions are developing advanced photonic chips that operate on the principles of light rather than electrical currents. This article discusses the limitations of […]
How to minimize design cycles for AI accelerators with advanced DFT and silicon bring-up
Design for testability (DFT) embeds testable features into an integrated circuit (IC) during design, while silicon bring-up initiates chip evaluation and debugging. Streamlining these sequential processes minimizes design cycles and shortens time-to-market (TTM) for advanced artificial intelligence (AI) accelerators. This article explores the complexities of AI chip design and outlines strategies for optimizing DFT and […]
